Variable digital delay lines based on a multi-tap architecture implemented in silicon have a large dynamic range of operation and are generally selected for such applications as clock skew compensation, data recovery, delay and time measurements, as well as signal synthesis. As the performance specifications for these applications continue to stress critical design parameters such as power dissipation requirements, delay-tap resolution, and overall physical size, the known conventional architecture has become increasingly limited.
The architecture of the conventional variable multi-tap digital silicon-based delay line comprises a delay chain connected to a 1-of-N multiplexer output circuit. Each of the inputs of the 1-of-N multiplexer output circuit is connected to a tap of the delay chain. A signal applied to the input of the delay chain propagates down the length of the delay chain and is sampled at a particular tap using the tap-select 1-of-N multiplexer output circuit. The final delay contribution is equal to the total number of delay stages the signal has passed through plus the propagation delay of the multiplexer output circuit.
Considered in more detail, as shown in FIG. 1, the conventional multi-tap variable digital delay line utilizes tap decode logic 10 comprising a 1-of-N input selector connected to an inverter delay chain 12. As part of the configuration, a set of tap-to-OR-tree gates 14 is included to reduce tap loading and fan out to a measurement latch 20 and balanced OR tree 16. Also included is a set of measurement gates 18 to enable the tap-to-measurement-latch path during a delay measurement operation. The balanced OR tree 16 comprises a 1-of-N multiplexer output circuit to route the signal from the selected tap of the delay chain 12 to the final output.
The conventional multi-tap variable digital delay line has several critical disadvantages. First, the delay of the 1-of-N multiplexer output circuit is large and is a significant portion of the latency of the overall structure. Second, in general, the resolution of this structure is limited to a buffer, or twice the inverter delay. Increasing the resolution down to a single inverter delay requires the addition of another multiplexer structure or the addition of an inverter string offset by an inverter delay with a significant increase in power consumption. Third, with the 1-of-N multiplexer output circuit placed after the delay chain, the delay associated with the multiplexer output circuit cannot be directly included in delay calculation, nor does its placement allow its delay to be automatically included in de-skew or other latency-sensitive applications. Other disadvantages are the overall size of the 1-of-N multiplexer output circuit and power consumed. Thus, the limiting aspects of the conventional multi-tap variable digital delay line are primarily attributable to the 1-of-N multiplexer output circuit.
It would therefore be desirable to provide a delay line architecture having improved delay-tap resolution. Additionally, it would be desirable to provide a delay line architecture that eliminates the need for a tap-select multiplexer output circuit, thus avoiding the added latency, reducing the overall size of the structure, and decreasing the amount of power consumption. Such a delay line architecture would have significant advantages.